DV - Staff Verification Engineer - Serdes
Eliyan · Bay Area, Vancouver or Toronto
Extracted from the posting
Staff verification engineer at Eliyan, an early-stage chiplet startup, leading verification of SerDes, PHYs, and DSP blocks. Owns TX/RX equalization and CDR verification, writes UVM/SystemVerilog testbenches, and runs GLS and formal (Jasper Gold or vc-formal).
Join the leading chiplet startup! As an Eliyan Staff Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead the verification of Serdes. You will be developing state-of-the-art testbenches and unit/chip level test cases for best-in-class PHYs. You will own verification of TX/RX equalization and CDR. This is a hands-on technical leadership role. You'll define PHY verification architecture, write UVM/SV testbenches, and make sure that designs are bug free. You will work with a cross-functional team of experts. We offer a fun work environment with excellent benefits. ONSITE M-F.
