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Senior Standard Cell Design Engineer

JRC Careers 路 St. Paul; Sunnyvale, California, United States

Extracted from the posting

Base
Not stated
Remote
On-site
Visa
Must be eligible to obtain U.S. security clearance
Stack
VLSI, CAD tools

Senior Standard Cell Design Engineer for radiation-hardened microelectronics at JRC's Semiconductor Technology team. You'll develop LEAP Standard Cell Libraries across advanced foundry nodes, optimize PPA in harsh environments, and collaborate with foundry partners. The role involves SPICE simulation, circuit design, and reliability modeling using tools like Virtuoso and Spectre.


Who We Are (video)

At JRC, we tackle some of the toughest challenges faced by the Department of Defense (DoD) and other government agencies. Our expertise in engineering innovation and semiconductor technologies allows us to deliver mission-critical microelectronics solutions, aerospace systems engineering, and cutting-edge research and development. By joining JRC, you鈥檒l be part of a team that supports strategic deterrence and defense missions, playing a crucial role in ensuring the safety and security of the United States and its allies.


馃殌

Join JRC's Semiconductor Technology Team!

Join JRC鈥檚 cutting鈥慹dge Semiconductor Technology team as a Senior Standard Cell Design Engineer and lead the development of next鈥慻eneration radiation鈥慼ardened microelectronics. In this high鈥慽mpact role, you鈥檒l drive the technical execution of our LEAP Standard Cell Library, shape proprietary simulation tools for radiation鈥慽nduced reliability prediction, and collaborate closely with foundry partners on advanced-node designs.

You鈥檒l architect and validate new standard cells across multiple technologies, optimize PPA under extreme conditions, support MPW test鈥慶hip runs, and advance key automation and modeling capabilities. This role is ideal for an engineer who thrives at the intersection of device physics, circuit design, and reliability modeling.

We鈥檙e looking for someone with deep semiconductor design expertise, hands鈥憃n experience in standard cell and library development, strong simulation and characterization skills, and eligibility for a U.S. security clearance. Experience with advanced nodes, RHBD techniques, memory design, and characterization tools is a strong plus.

If you鈥檙e excited about building resilient microelectronics that power mission鈥慶ritical systems, we鈥檇 love to meet you.

馃捈What You'll Do

  • Execute the design and development of Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.
  • Generate and validate new standard cells and IP, including combinatorial logic, sequential logic, and power management cells.
  • Leverage in-house software and industry-standard SPICE tools to calculate radiation-induced error rates to ensure circuit resilience.
  • Execute advanced library characterizations to optimize Power, Performance, and Area (PPA) in harsh environments.
  • Collaborate directly with external foundry partners on Multi-Product Wafer (MPW) runs and provide technical design support to customers.
  • Contribute to the development of proprietary simulation software and automation scripts to improve reliability prediction.

馃What You Bring

  • Master鈥檚 degree with 2+ years of direct industry experience, OR a Bachelor鈥檚 degree with 4+ years of experience.
  • Must be eligible to obtain a U.S. security clearance due to the nature of defense-related projects.
  • Deep knowledge of semiconductor design methodologies and principles.
  • Hands-on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)
  • Demonstrated experience being involved in test-chip designs and MPW execution.
  • Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
  • Extensive experience with simulation tools, specifically for library characterization.

猸怋onus Points

  • Master鈥檚 degree with 5+ years of experience, or Bachelor鈥檚 with 7+ years in industry.
  • Hands鈥憃n design experience with GAA nodes (e.g., Intel 18A), including device architecture and design鈥憆ule familiarity.
  • Proven background in SRAM/NVM bitcell design and/or memory compiler development.
  • Practical experience with Liberate, PrimeLib, and SiSmart for characterization and modeling.
  • Expertise in RHBD for SEE/SEU mitigation, plus proficiency in C++ and scripting (Python/TCL) across advanced nodes (FinFET, GAA, SOI).


At JRC we offer...

  • A competitive compensation package
  • An exceptional employee benefits program, providing support for our team members' well-being and success
  • The chance to contribute to a high-profile Department of Defense programs and make a positive impact
  • A collaborative work environment where teamwork, creativity, and innovation thrive
  • Opportunities for professional growth and development, helping you advance your career


Technologies

VLSICAD tools
JRC Careers
JRC Careers

Job details

TypeFull-time
Work ModeOn-site
LevelSenior
Location馃嚭馃嚫Sunnyvale, CA馃嚭馃嚫St. Paul, MN
PostedOct 05, 2026
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