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Sr Staff/Principal CAD and Design Methodology engineer defining multi-vendor RTL-to-GDSII flows for advanced SoCs across Intel, TSMC, Samsung and GlobalFoundries nodes. Tools named include Synopsys, Cadence and Siemens EDA, with UPF/CPF low-power flows and clocking methodology.
ABOUT THE ROLE
As a Sr Staff / Principal CAD & Design Methodology Engineer, you will be the technical architect of RTL-to-GDSII flows and digital design infrastructure for advanced SoC products. You will define and deploy multi-vendor, multi-foundry design methodology platforms, lead hierarchical SoC implementation strategies, and drive low-power chiplet products. You will own the R2G (RTL-to-GDSII) system architecture spanning Intel, TSMC, Samsung, and GlobalFoundries nodes — enabling scalable, high-quality tapeouts across diverse product classes.
