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About OLIX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

The Role

We are designing silicon for a new and innovative breakthrough AI computing solution using optics and high-speed interconnect. Verifying the mixed-signal subsystems of this solution is one of the hardest and highest-leverage problems in the design flow and it is where this role sits. As a Senior Mixed-Signal Verification Engineer, you will own the verification of analog and mixed-signal blocks across our high-speed IO RX/TX chains - CDRs, phase interpolators and clock generation, DFE/CTLE equalization, samplers and slicers, deserializers, and the digital control loops that wrap around them. You will work at the boundary where analog behavior meets digital control, building the models, environments, and methodology that let us find bugs in silicon-accurate simulation rather than in the lab.

Responsibilities

Own the verification strategy and test plan for our mixed-signal subsystems, from block level through subsystem and top-level integration.

Define the modeling approach and fidelity tiers - decide what gets a real-number model, what needs Verilog-AMS, and where transistor-level co-sim is required - and document the accuracy/runtime trade-offs.

Develop and validate analog behavioral models against transistor-level references, owning the model-vs-schematic equivalence checks that keep the abstraction honest.

Build self-checking testbenches and reusable verification components for analog/digital interactions: CDR lock, adaptation and calibration loop convergence, mode and power-state transitions, clock dividers, deserializers, and clock-domain crossings.

Drive AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and own their setup, performance, and runtime trade-offs.

Define functional coverage and assertions that target analog corner behavior - saturation, overflow, polarity, loop stability, settling - not just digital state.

About OLIX

The Role

Responsibilities

Own the verification strategy and test plan for our mixed-signal subsystems, from block level through subsystem and top-level integration.
Define the modeling approach and fidelity tiers - decide what gets a real-number model, what needs Verilog-AMS, and where transistor-level co-sim is required - and document the accuracy/runtime trade-offs.
Develop and validate analog behavioral models against transistor-level references, owning the model-vs-schematic equivalence checks that keep the abstraction honest.
Build self-checking testbenches and reusable verification components for analog/digital interactions: CDR lock, adaptation and calibration loop convergence, mode and power-state transitions, clock dividers, deserializers, and clock-domain crossings.
Drive AMS co-simulation flows (Spice/FastSpice coupled with digital simulators) and own their setup, performance, and runtime trade-offs.
Define functional coverage and assertions that target analog corner behavior - saturation, overflow, polarity, loop stability, settling - not just digital state.

AMS Engineer

IC Design Verification Engineer

Verification Lead (Lead DV)

AMS Engineer

Extracted from the posting

TL;DR

The full posting

About OLIX

The Role

Responsibilities

Skills & Experience

Nice to have

Compensation & Equity