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Member of Technical Staff role building functional and performance models for a scale-up network-attached memory expansion device for AI accelerators. Models span rack-scale and chip-level data movement, from software memory access patterns down to on-device memory channels. The role identifies bottlenecks across compute, memory and interconnects, and requires 5-10+ years in performance modeling of NICs, CXL memory expansion, IPU/DPU or NoC.
The biggest bottleneck in AI systems today is memory. Chips compute faster than they can be fed data—a problem known as the memory wall—and Netpreme is building the solution that allows AI memory to scale independently of AI compute. Our approach spans the full stack, from a proprietary memory management framework at the XPU kernel and OS levels to X-Mem™, the world’s first Memory Processing Unit (MPU) silicon. Founded by MIT researchers at the intersection of optical networking, ML systems, and GPU kernel optimization, we’re based in Cambridge, MA, and Santa Clara, CA. We’re looking for people who want to own hard problems end to end—and help shape the next generation of AI systems.
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We are seeking a Member of Technical Staff, Functional and Performance Modeling to develop functional and performance models for our scale-up network-attached memory expansion device for AI accelerators.
You’ll work as part of our silicon architecture team to perform functional and performance modeling. You should have experience exploring design tradeoffs, validating performance assumptions, and identifying bottlenecks early in the development cycle. This role is well-suited for engineers who enjoy reasoning from first principles, working with incomplete information, and co-exploring the design space as hardware and software evolve together.
This role will be performed onsite from one of our offices in Santa Clara, CA or Boston, MA.
