Own digital functional blocks from microarchitecture through synthesizable RTL, integration, and implementation, including lint, CDC/RDC, synthesis, timing closure, and LEC. Work with verification, DFT, physical design, and firmware teams. Requires 6+ years of digital IC design with Verilog or SystemVerilog and Synopsys or Cadence tools.
Senior or Staff Digital Design Engineer
Reports To: Head of Engineering
About Us
Powerlattice is a well-funded semiconductor start-up company backed by leading Silicon Valley venture capital firms. We are developing groundbreaking chiplet power delivery technology that will transform how high-performance processors are powered, enabling the next generation of AI and advanced computing.
About the Role
We are seeking an experienced and hands-on Senior Digital Design Engineer to contribute to the design and implementation of complex digital systems and SoC components. This role offers the opportunity to own significant functional blocks from microarchitecture through RTL development, integration, and implementation while collaborating closely with verification, physical design, and DFT teams.
The ideal candidate is passionate about digital design, enjoys solving challenging technical problems, and thrives in a collaborative startup environment where individual contributions have a direct impact on product success.
Key Responsibilities
Digital Design & RTL Development
Integration & Implementation
Design Quality
Cross-Functional Collaboration
Qualifications
This is a Hybrid role requiring 3 days a week onsite at our HQ’s in Vancouver, WA (Greater Portland Area) or Chandler, AZ. While we are primarily seeking candidates in HQ-Vancouver and Chandler, remote flexibility may be considered for exceptional candidates in Silicon Valley, CA.
Preferred
Compensation & Benefits
Anticipated annual base salary for Member of Technical Staff: $150,000 - $200,000
